1. Field of the Invention
This invention relates to computer memory systems and, more particularly, to techniques for reducing power consumption of computer memory systems.
2. Description of the Related Art
Evolving standards for computer memory systems have lead to systems that include greater numbers of higher capacity memory devices. Consequently, computer memory systems have seen an increase in power consumption. One technology in particular, the Fully Buffered Dual Inline Memory Module (FBDIMM), achieves very high memory density by allowing memory modules to be connected in series, rather than in parallel. A parallel architecture suffers from the problem that each additional memory module increases the electrical loading on the parallel data and address buses. The serial point-to-point architecture used by FB-DIMMs overcomes the electrical loading problem since electrical loading is not changed when another module is added. However, the resulting increase in the number of modules that the system can support increases the power consumption of the memory system.
In addition to the above considerations, much of the power dissipated in an FB-DIMM is consumed in the transmitter and receiver circuitry of the bus interfaces. FB-DIMMs are coupled to the serial bus through an Advanced Memory Buffer (AMB) that includes the transmitter and receiver circuitry. In order to facilitate a variety of low-power operating modes, the FB-DIMM specification allows for an AMB's transmitter and receiver circuitry to be placed in a low latency standby (L0s) state. In the L0s state, the transmitter and receiver circuitry for the local FB-DIMM is disabled to save power while signals are allowed to pass through to subsequent FB-DIMMs further down the bus. However, the FB-DIMM specification does not provide guidance on when or through what algorithm to place an AMB in the L0s state. Consequently, what is needed is a mechanism to reduce the power dissipation of individual memory modules within a memory system by selectively placing the AMB's in the L0s state without significantly reducing access speed or increasing latency.